Introduction

This help document is intended to provide in-depth information and reference material specific to your digitizer product.

For information on getting started with your digitizer, please refer to the Startup Guide which was delivered with your product or may be downloaded from the Keysight Technologies website.

Contents:

Notices & General Information

Get More Assistance

TIP: Help Search Techniques

Related Documentation

Full Product Family Listing & Cross-reference tables

Introduction

Front Panel Features

Channel Input

Data Acquisition

Trigger

External Clock and Reference

Calibration

Trigger Output

Multi-Purpose Inputs and Outputs

Signal Processing (Firmware Options)

Triggered Simultaneous Acquisition and Readout (TSR)

Digital Down-Conversion Mode (DDC / LDC)

Custom Firmware (FDK)

Application Options

High Fidelity Digitizer (BB1)

Digitizer Streaming (CB0)

Digital Down-Converter Streaming (CB1/CB2)

Electrical, Environmental & Physical Specifications

Programming Information

Initial Configuration

How To ...

ApplySetup

Known issues for MATLAB users

Utilities

Firmware Upgrade Utility

Option Upgrade Utility

FAQs

© Keysight Technologies 2016

Part No: M9203-90005

Avril, 2016


Notices

© Keysight Technologies, 2016

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Keysight Technologies, Inc. as governed by United States and international copyright laws.

Manual Part Number

M9203-90005

Support

To contact Keysight for sales and technical support, refer to the “support” links on the following Keysight web resources:

www.keysight.com/find/digitizers - Home page for the entire range of Keysight modular digitizer products.

www.keysight.com/find/assist - Worldwide contact information for repair and service.

www.keysight.com/find/tips - Information on preventing damage to your Keysight equipment.

Regulatory Compliance

This product has been designed and tested in accordance with accepted industry standards, and has been supplied in a safe condition. To review the Declaration of Conformity, go to http://www.keysight.com/go/conformity .

Warranty

The material contained in this document is provided “as is,” and is subject to being changed, without notice, in future editions. Further, to the maximum extent permitted by applicable law, Keysight disclaims all warranties, either express or implied, with regard to this manual and any information contained herein, including but not limited to the implied warranties of merchantability and fitness for a particular purpose. Keysight shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein. Should Keysight and the user have a separate written agreement with warranty terms covering the material in this document that conflict with these terms, the warranty terms in the separate agreement shall control.

Keysight Technologies does not warrant third-party system-level (combination of chassis, controllers, modules, etc.) performance, safety, or regulatory compliance, unless specifically stated.

Technology Licenses

The hardware and/or software described in this document are furnished under a license and may be used or copied only in accordance with the terms of such license.

U.S. Government Rights

The Software is “commercial computer software,” as defined by Federal Acquisition Regulation (“FAR”) 2.101. Pursuant to FAR 12.212 and 27.405-3 and Department of Defense FAR Supplement (“DFARS”) 227.7202, the U.S. government acquires commercial computer software under the same terms by which the software is customarily provided to the public. Accordingly, Keysight provides the Software to U.S. government customers under its standard commercial license, which is embodied in its End User License Agreement (EULA), a copy of which can be found at http://www.keysight.com/find/sweula. The license set forth in the EULA represents the exclusive authority by which the U.S. government may use, modify, distribute, or disclose the Software. The EULA and the license set forth therein, does not require or permit, among other things, that Keysight: (1) Furnish technical information related to commercial computer software or commercial computer software documentation that is not customarily provided to the public; or (2) Relinquish to, or otherwise provide, the government rights in excess of these rights customarily provided to the public to use, modify, reproduce, release, perform, display, or disclose commercial computer software or commercial computer software documentation. No additional government requirements beyond those set forth in the EULA shall apply, except to the extent that those terms, rights, or licenses are explicitly required from all providers of commercial computer software pursuant to the FAR and the DFARS and are set forth specifically in writing elsewhere in the EULA. Keysight shall be under no obligation to update, revise or otherwise modify the Software. With respect to any technical data as defined by FAR 2.101, pursuant to FAR 12.211 and 27.404.2 and DFARS 227.7102, the U.S. government acquires no greater than Limited Rights as defined in FAR 27.401 or DFAR 227.7103-5 (c), as applicable in any technical data.

Conventions Used in this Document

The following conventions are used in this document:

A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in personal injury or death. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.

A Caution notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met

This is a note, drawing the reader's attention to important information, caveats, etc.

'Italic' text denotes a reference to a quoted name or entity. e.g."Press the 'Run' button."

Bold Italic text is used to emphasize an important action point in the text. e.g. "Open the View menu and select the All option."

mono text is used for sections of code, programming examples and operating system commands. e.g. "Type the command >> Run -all"

Underlined Italic text denotes paths or file names. e.g. "The file is located in the folder, e.g...\Keysight\MD2\.."

Safety Notices

The following safety precautions should be observed before using this product and any associated instrumentation.

This product is intended for use by qualified personnel who recognize shock hazards and are familiar with the safety precautions required to avoid possible injury. Read and follow all installation, operation, and maintenance information carefully before using the product.

If this product is not used as specified, the protection provided by the equipment could be impaired. This product must be used in a normal condition (in which all means for protection are intact) only.

The types of product users are:

  • Responsible body is the individual or group responsible for the use and maintenance of equipment, for ensuring that the equipment is operated within its specifications and operating limits, and for ensuring operators are adequately trained.
  • Operators use the product for its intended function. They must be trained in electrical safety procedures and proper use of the instrument. They must be protected from electric shock and contact with hazardous live circuits.
  • Maintenance personnel perform routine procedures on the product to keep it operating properly (for example, setting the line voltage or replacing consumable materials). Maintenance procedures are described in the user documentation. The procedures explicitly state if the operator may perform them. Otherwise, they should be performed only by service personnel.
  • Service personnel are trained to work on live circuits, perform safe installations, and repair products. Only properly trained service personnel may perform installation and service procedures.

Operator is responsible to maintain safe operating conditions. To ensure safe operating conditions, modules should not be operated beyond the full temperature range specified in the Environmental and physical specification. Exceeding safe operating conditions can result in shorter lifespans, improper module performance and user safety issues. When the modules are in use and operation within the specified full temperature range is not maintained, module surface temperatures may exceed safe handling conditions which can cause discomfort or burns if touched. In the event of a module exceeding the full temperature range, always allow the module to cool before touching or removing modules from chassis.

Keysight products are designed for use with electrical signals that are rated Measurement Category I and Measurement Category II, as described in the International Electrotechnical Commission (IEC) Standard IEC 60664. Most measurement, control, and data I/O signals are Measurement Category I and must not be directly connected to mains voltage or to voltage sources with high transient over-voltages. Measurement Category II connections require protection for high transient over-voltages often associated with local AC mains connections. Assume all measurement, control, and data I/O connections are for connection to Category I sources unless otherwise marked or described in the user documentation.

Exercise extreme caution when a shock hazard is present. Lethal voltage may be present on cable connector jacks or test fixtures. The American National Standards Institute (ANSI) states that a shock hazard exists when voltage levels greater than 30V RMS, 42.4V peak, or 60VDC are present. A good safety practice is to expect that hazardous voltage is present in any unknown circuit before measuring.

Operators of this product must be protected from electric shock at all times. The responsible body must ensure that operators are prevented access and/or insulated from every connection point. In some cases, connections must be exposed to potential human contact. Product operators in these circumstances must be trained to protect themselves from the risk of electric shock. If the circuit is capable of operating at or above 1000V, no conductive part of the circuit may be exposed.

Do not connect switching cards directly to unlimited power circuits. They are intended to be used with impedance-limited sources. NEVER connect switching cards directly to AC mains. When connecting sources to switching cards, install protective devices to limit fault current and voltage to the card.

Before operating an instrument, ensure that the line cord is connected to a properly-grounded power receptacle. Inspect the connecting cables, test leads, and jumpers for possible wear, cracks, or breaks before each use.

When installing equipment where access to the main power cord is restricted, such as rack mounting, a separate main input power disconnect device must be provided in close proximity to the equipment and within easy reach of the operator.

For maximum safety, do not touch the product, test cables, or any other instruments while power is applied to the circuit under test. ALWAYS remove power from the entire test system and discharge any capacitors before: connecting or disconnecting cables or jumpers, installing or removing switching cards, or making internal changes, such as installing or removing jumpers.

Do not touch any object that could provide a current path to the common side of the circuit under test or power line (earth) ground. Always make measurements with dry hands while standing on a dry, insulated surface capable of withstanding the voltage being measured.

The instrument and accessories must be used in accordance with its specifications and operating instructions, or the safety of the equipment may be impaired.

Do not exceed the maximum signal levels of the instruments and accessories, as defined in the specifications and operating information, and as shown on the instrument or test fixture panels, or switching card.

When fuses are used in a product, replace with the same type and rating for continued protection against fire hazard.

Chassis connections must only be used as shield connections for measuring circuits, NOT as safety earth ground connections.

If you are using a test fixture, keep the lid closed while power is applied to the device under test. Safe operation requires the use of a lid interlock.

Instrumentation and accessories shall not be connected to humans.

Before performing any maintenance, disconnect the line cord and all test cables.

To maintain protection from electric shock and fire, replacement components in mains circuits – including the power transformer, test leads, and input jacks – must be purchased from Keysight. Standard fuses with applicable national safety approvals may be used if the rating and type are the same. Other components that are not safety-related may be purchased from other suppliers as long as they are equivalent to the original component (note that selected parts should be purchased only through Keysight to maintain accuracy and functionality of the product). If you are unsure about the applicability of a replacement component, call an Keysight office for information.

No operator serviceable parts inside. Refer servicing to qualified personnel. To prevent electrical shock do not remove covers. For continued protection against fire hazard, replace fuse with same type and rating.

PRODUCT MARKINGS:

The CE mark is a registered trademark of the European Community.

Australian Communication and Media Authority mark to indicate regulatory compliance as a registered supplier.

This symbol indicates product compliance with the Canadian Interference-Causing Equipment Standard (ICES-001). It also identifies the product is an Industrial Scientific and Medical Group 1 Class A product (CISPR 11, Clause 4).

South Korean Class A EMC Declaration. this equipment is Class A suitable for professional use and is for use in electromagnetic environments outside of the home.

A 급 기기 ( 업무용 방송통신기자재 ) 이 기기는 업무용 (A 급 ) 전자파적합기기로서 판 매자 또는 사용자는 이 점을 주 의하시기 바라 며 , 가정외의 지역에서 사용하는 것을 목적으 로 합니다 .

This product complies with the WEEE Directive marketing requirement. The affixed product label (above) indicates that you must not discard this electrical/electronic product in domestic household waste. Product Category: With reference to the equipment types in the WEEE directive Annex 1, this product is classified as “Monitoring and Control instrumentation” product. Do not dispose in domestic household waste. To return unwanted products, contact your local Keysight office, or for more information see http://about.keysight.com/en/companyinfo/environment/takeback.shtml.

This symbol on an instrument means caution, risk of danger. You should refer to the operating instructions located in the user documentation in all cases where the symbol is marked on the instrument.

This symbol indicates the time period during which no hazardous or toxic substance elements are expected to leak or deteriorate during normal use. Forty years is the expected useful life of the product.

ESD Sensitive Device

This symbol indicates the instrument is sensitive to electrostatic discharge (ESD). ESD can damage the highly sensitive components in your instrument. ESD damage is most likely to occur as the module is being installed or when cables are connected or disconnected. Protect the circuits from ESD damage by wearing a grounding strap that provides a high resistance path to ground. Alternatively, ground yourself to discharge any built-up static charge by touching the outer shell of any grounded instrument chassis before touching the port connectors.

This symbol denotes a hot surface. The side cover of the module will be hot after use and should be allowed to cool for several minutes.

Cleaning Precautions:

To prevent electrical shock, disconnect the Keysight Technologies instrument from mains before cleaning. Use a dry cloth or one slightly dampened with water to clean the external case parts. Do not attempt to clean internally. To clean the connectors, use alcohol in a well-ventilated area. Allow all residual alcohol moisture to evaporate, and the fumes to dissipate prior to energizing the instrument.

Definitions for specifications

Specifications describe the warranted performance of calibrated instruments that have been stored for a minimum of 2 hours within the operating temperature range of 0 to 45 °C, unless otherwise stated, and after a 45 minute warm-up period. Data represented in this document are not specifications unless otherwise noted.

Characteristics describe product performance that is useful in the application of the product, but that is not covered by the product warranty. Characteristics are often referred to as Typical or Nominal values.

  • Typical describes characteristic performance, which 80% of instruments will meet when operated over a 20 to 30 °C temperature range. Typical performance is not warranted.
  • Nominal describes representative performance that is useful in the application of the product when operated over a 20 to 30 °C temperature range. Nominal performance is not warranted.


Get More Assistance

  • Related Documentation
  • Go to M9203A Website: www.keysight.com/find/M9203A
  • Go to High Speed Digitizer Product Website
  • Go to Support Website


View Product Information on Keysight.com

To go to the Product Website, click on the following link:

http://www.keysight.com/find/digitizers


View Support Information on Keysight.com

To go to the Support Website, click the following link:

http://www.keysight.com/find/assist


TIP: Help Search Tricks

In the help system, a basic search of topics consists of the word or phrase that you want to find. You can, however, improve your search results by using wildcard expressions, nested expressions, Boolean operators, and searching similar word matches, previous results, and topic titles only.

Performing a Basic Full-Text Search

  1. In the navigation pane, click the Search tab and then type the word or phrase that you want to find. Use the right-arrow button to add Boolean operators to your search.
  • Click List Topics.Your search will return the first 500 hits. If you want to sort the topic list, click Title, Location, or Rank.
  • Highlight the topic that you want, and then click Display You can also display any topic by double-clicking it.

Refining a Your Search

You can refine a basic search by using wildcard expressions, nested expressions, and Boolean operators. You can also search only on the previous results list, request similar word matches, or search only the titles of topics in the table of contents.

  • To refine a search to include just the last group of topics you searched, select the Search previous results check box.
  • To match similar spellings in a full-text search, select the Match similar words check box.

When Match similar words is selected, the viewer matches minor grammatical variations of the word or phrase you entered, as well as the word or phrase itself. For example, if you entered "test" and selected this box, the Library viewer would find "test", "tests", and "testing". This option is independent of other options or syntax. If you do a titles-only search, variations in titles will be matched. If you use quotes (or any other query operator) any variation of the word can appear; for example, "installed module" will also match "installing module".

  • To search for words in document titles only, select the Search titles only check box.

Search Syntax

The basic rules for formulating queries are as follows:

  • Searches are not case-sensitive, so you can type your search in uppercase or lowercase characters.
  • You can search for any combination of letters (a–z) and numbers (0–9). You cannot search for single letters (a, b, c, etc.) and the following reserved words: an, and, as, at, be, but, by, do, for, from, have, he, in, it, not, of, on, or, she, that, the, there, they, this, to, we, which, with, you.
  • Punctuation marks such as the period (.), colon (:), semicolon (;), comma (,), and hyphen (-) are ignored during a search.
  • Group the elements of your search using "double quotes" or (parentheses). You cannot search for quotation marks.
If you are searching for a filename with an extension, you should group the entire string in double quotes ("filename.ext"). Otherwise, the search will treat the period as an OR operator.

Words, Phrases, and Wildcards

You can search for words or phrases and use wildcard expressions. The table below describes the results of these different kinds of searches.

Search for | Example | Results
Single word | Calibrate | Topics that contain the word "calibrate." (You will also find its grammatical variations, such as "calibration" and"calibrated".)
Phrase | "saved configuration" -or- 'saved configuration' | Topics that contain the literal phrase "saved configuration" and all its grammatical variations. Without the quotation marks, the query is equivalent to specifying a saved AND configuration, which will find topics containing both of the individual words, instead of the phrase.
Wildcard expressions | Meas* | Topics that contain the terms "Meas," "measure," "measurement," and so on. The asterisk cannot be the only character in the words.
 | 89?00 | Topics that contain the terms "89500," "89600," "89700," and so on. The question mark cannot be the only character in the term.
 | *936* | Topics that contain the terms "936." "45936,""M9360A," "93600" and so on.
 | *93 | Topics that contain the terms "293," "393," "x93," "ABCD393," "8093," and so on.

Operators: AND, OR, NOT, and NEAR

The AND, OR, NOT, and NEAR operators allow you to refine your search. The following table shows how to use each of these operators.

Search for | Example | Results
Both terms in the same topic | performance AND verification -or- performance & verification | Topics containing both the words "performance" and "verification."
Either term in a topic | front OR panel -or- front | panel | Topics containing either the word "front" or the word "panel."
The first term without the second term | system NOT requirements -or_ system ! requirements | Topics containing the word "system," but not the word "requirements."
Both terms in the same topic, close together | install NEAR hardware | Topics containing the word "install" within eight words of the word "hardware."

Rules for Nested Expressions

The basic rules for searching topics using nested expressions are as follows:

  • You can use parentheses to nest expressions within a query. The expressions in parentheses are evaluated before the rest of the query.
  • If a query does not contain a nested expression, it is evaluateds from left to right. For example, "Instrument NOT system OR calibration" finds topics containing the term "instrument" without the term "system", or topics containing the term "instrument" and not "calibration". (On the other hand, "instrument NOT (system OR calibration)" finds topics containing the term "instrument" without either of the terms "system" or "calibration".)
  • Nesting allows you to create more complex search expressions. For example, "instrument AND ((system OR calibration) NEAR performance)" finds topics containing the term "instrument" along with the terms "system" and "performance" close together, or containing "instrument" along with the terms "calibration" and "performance" close together.
  • You cannot nest expressions more than five levels deep.


Related Documentation

Documentation Access Map

All documentation relating to your Keysight Technologies digitizer may be found either from the DVDs supplied with your product, or from the Keysight

Documentation

If you have run the Keysight software installer for your product on your PC, the related product documentation has been installed to your hard drive. Otherwise these documents are available for download from the Keysight Technologies website.

Document | Description
Startup Guide | Includes procedures to help you to unpack, inspect, install (software and hardware), perform instrument connections, verify operation, and troubleshoot your product.
User Manual | Provides in-depth information and reference material specific to your digitizer product
Data Sheet | In addition to a detailed product introduction, the data sheet supplies full product specifications.
Soft Front Panel (help system) | Provides information on the use of the Soft Front Panel.
LabVIEW Driver reference (help system) | Provides detailed documentation of the LabVIEW G driver API functions.
IVI Driver reference (help system) | Provides detailed documentation of the IVI-COM and IVI-C driver API functions, as well as information to help you get started with using the IVI drivers in your application development environment.


Full Product Family Listing & Cross-reference tables

This help file has been organized to allow easy access by arranging the product lines under their form factors listed below:

PCI Express Digitizers

The products in the industry standard PCI Express format benefit from the very high data transfer rates of the PCIe interface, and occupying a single slot in a host PC. They also feature programmable on-board processing capabilities.

Keysight Model Number | Model Name
U1084A | 8-bit PCIe High-Speed PCIe Digitizer with on-board signal processing
U5303A | 12-bit PCIe High-speed Digitizer with on-board signal processing
U5309A | 8-bit PCIe High-Speed Digitizer with on-board signal processing

Note: That the U1084A product utilizes PCIe Gen 1.1 and a x4 slot, whereas the U53xx series support PCIe Gen 2.0 and a x8 slot.

PXI Express High-Speed Digitizers

This product line is composed of Keysight PXI Express new generation of high-speed digitizers.

These are PXI Express compliant, using either a PXIe or PXIe Hybrid slot. Designed to benefit from fast data interfaces, the products can be integrated with other test and automation modules in PXIe and Hybrid chassis slots. The PXI format offers high performance in a small, rugged package. It is an ideal deployment platform for many automated test systems

Keysight Model Number | Model Name
M9202A | PXI Express 12-bit Wideband IF Digitizer
U5203A | PXI Express 12-bit High-Speed Digitizer
M9203A | PXI Express 12-bit High-Speed Digitizer/ Wideband Digital Receiver
AXIe Digitizers

This product line is composed of Keysight Technologies new generation of AXIe Digitizers.

The AXIe format offers high performance in a highly scalable package, offering at least twice the channel density of currently available comparable solutions. Making it ideally suited to large scale experiments in applied physics, such as particle physics, nuclear fusion, hydrodynamics or microwave radio astronomy.

Keysight Model Number | Model Name
M9703A | AXIe 12-bit, 8 channels Wideband Digitizer
M9703B | AXIe 12-bit, 8 channels Wideband Digitizer
M9709A | AXIe 8-bit, 32 channels Wideband Digitizer


Keysight M9203A PCIe Digitizer Introduction

Overview

The M9203A is a very fast PXIe Digitizer featuring wide analog bandwidth, making it ideal for Automated Test Equipment (ATE) in Aerospace & Defense applications such as Military Mobile Repair Stations, Radar Test or any application requiring wideband signal capture and at the same time very high dynamic range.

Product description

The M9203A is a dual-slot 3U PXIe 12-bit Wideband Digitizer running at 3.2 GS/s, with up to 2 GHz instantaneous analog bandwidth and providing a large DDR3 acquisition memory up to 4 GB. The M9203A features a Xilinx Virtex-6 FPGA Closed Field Programmable Gate Array that can implement different functionalities depending on which firmware option you choose.

At the heart of the M9203A is a data processing unit (DPU Closed Digital Processing Unit) based on the powerful Xilinx Virtex-6 FPGA Closed Field Programmable Gate Array. This DPU Closed Digital Processing Unit is responsible for controlling the module functionality, data flow and real-time signal processing. This powerful feature allows data reduction and storage to be carried out at the digitizer level, minimizing transfer volumes and speeding-up analysis. The available U5340A FPGA Closed Field Programmable Gate Array development kit provides a direct interface to the digitizer hardware elements.

Figure 1 - M9203A block diagram

Most of the technical specifications concerning your particular digitizer are covered in this manual, however for the complete specifications please refer to the product's datasheet from the Keysight Technologies web site www.keysight.com/find/M9203A. These data sheets are available in pdf format and are best viewed using Adobe Acrobat software. If you have trouble accessing our web site, or viewing the data sheets, please contact your nearest sales office.


M9203A Front Panel Features

Front Panel Connectors
Connector | Type | Description
TRG IN | SMB male | External trigger input, 50 Ω DC terminated, ±5 V range.
IN 1, 2 SMA female

Analog signal inputs, DC-coupled and 50 Ω terminated.

The input Full Scale Ranges are selectable:

Voltage | 1 V FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. | 2 V FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.
Recommended maximum operating voltage | ±3 V | ±4.3 V
Clamp level | ±3.6 V | ±6.3 V
Absolute maximum DC voltage rating | ±4.6 V | ±5 V

Please refer to datasheet for details about input frequency range.

JTAG | Micro USB | Provides connection to the DPU Closed Digital Processing Unit for use with the U5340A FPGA Closed Field Programmable Gate Array Development Kit.
TRG OUT | SMB male | Trigger Out signal.
I/O 1, 2, 3 | MMCX female | User configurable Input / Output signal. 3.3 V CMOS and TTL compatible.
CLK IN | SMA female | External clock input. AC coupled and 50 Ω terminated, signal level: +5 to +15 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P). Frequency from 1.8 GHz to 3.2 GHz.
REF IN | SMB male | External reference clock input, AC coupled and 50 Ω terminated. It can accept a 100 MHz signal from -3 to +3 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P).

Digitizer can usually work with signals present at the external reference and clock inputs (REF IN and CLK IN). However, to ensure the best performance, or if the calibration is found to be unreliable, it is recommended to remove such signals when working with internal clock.

Front Panel LEDs

Indicator | Purpose | Color | State | Meaning
DPU Closed Digital Processing Unit | DPU Closed Digital Processing Unit status |  | Off | DPU Closed Digital Processing Unit is not configured
 |  |  | Green, blinking | Module initialization in progress
 |  |  | Green | Module OK (firmware not yet loaded)
 |  |  | White | DPU Closed Digital Processing Unit firmware loaded (ready)
STATUS | Module status |  | White, blinking | Firmware initialization in progress
 |  |  | Green, blinking | Module initialization in progress
 |  |  | Yellow, blinking | Warning
 |  |  | Red, blinking | Error
 |  |  | Green | OK (ready)

If warning or error status is observed, please try the following steps:

  • Power-cycle the chassis (If using a PCIe interface to external PC, observe the power sequence requirements)
  • If the error persists please contact Keysight technical support http://www.keysight.com/find/assist.

Adding custom stickers on digitizers

If user want to add a custom sticker on the module, the bottom cover of the digitizer could be used for this purpose.

In case of application of a custom sticker on the main shield and non-dedicated area, Keysight does not warranty cooling performance.


Channel Input Specifications

This section provides information and specifications regarding the input characteristics of the digitizer.

The M9203A provides two 1.6 GS/s, 12-bit DC-coupled channels. The two channels may be combined to form an interleaved channel at 3.2 GS/s (M9203A-INT option).

Channel Input

The M9203A has the following front end capabilities:

Coupling / Impedance | Full Scale Ranges (FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.) | Recommended maximum operating voltage | Clamp level | Absolute maximum DC voltage rating | Offset Adjustment
DC / 50 Ω | 1 V | ±3 V | ±3.6 V | ±4.6 V | ±2 x FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.
 | 2 V | ±4.3 V | ±6.3 V | ±5 V | ±2 x FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.

Impedance & Coupling

The input channel termination is 50 Ω. The input coupling is DC.

Input Protection

The input amplifiers are designed to accept signals below the level shown in the table.

Mezzanine Front-end

The front-end electronics are all mounted on a removable mezzanine card. In the event of accidental damage or as components fatigue over time (e.g. relays in high duty cycle automated testing applications), the mezzanine card allows for fast and efficient replacement.

Bandwidth and Rise Time

The bandwidth specification indicates the frequency at which an input signal will be attenuated by 3 dB (approximately 30% loss of amplitude).

Options |  |  | Input Frequency Range |  | BW Limiter selections
 |  |  | 1 V FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. | 2 V FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.
-F05 | -SR2 | — | DC to 650 MHz (typical) |  | No BW limiter
 |  | -INT
-F10 | -SR2 | — | DC to 1.9 GHz (typical) | DC to 2.0 GHz (typical) | 650 MHz
 |  | -INT | DC to 1.4 GHz (typical)

The bandwidth also affects the minimum rise and fall times that can be passed through the front-end electronics. A pulse with a very sharp edge will be observed to have a minimum rise time Tmin determined by the front-end electronics. In general a pulse with a given 10-90% rise time T10-90real will be observed with a lower value given by:

T10-90=T10-90real2+Tmin2

where Tmin(ns)≈0.35/BW(GHz).

Vertical Resolution

The M9203A PXIe Wideband Digitizer uses a 12-bit ADC Closed Analog to Digital Converter giving 4096 levels of ~0.25 mV average width when using the 1 V FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages.. The effective number of bits (ENOB Closed Effective Number Of Bits - expresses the quality of the ADC Closed Analog to Digital Converter quantification.) is greater than 9 (typical) over the full -F05 bandwidth .

Accuracy and Linearity

This digitizer uses low noise front-end electronics in order to ensure that voltage measurement is made with accuracy and precision. DC accuracy is typically 1%. DC gain accuracy is better than ±0.5 % in the 1 V range, and ±0.7 % in the 2 V range. Offset accuracy is better than ±0.5 % in the 1 V range, and ±1.5 % in the 2 V range.


Data Acquisition

The sections below summarize the data acquisition characteristics.

Sampling Rate

The M9203A Digitizer contains an analog-to-digital conversion (ADC Closed Analog to Digital Converter) system that can sample waveforms, in a real time sampling mode, at rates shown in the table below. The maximum sampling rate shown above is achieved by combining the two channels.

Model | Option | Max. Sampling Rate | Available Channels | Resolution | Acquisition Modes
M9203A | -SR2 | 1.6 GS/s | 2 | 12 bits | Single or multi-record (up to 131'072 records) or continuous (depends on firmware options)
 | -SR2 and -INT | 3.2 GS/s | 1

The External Clock can be used to vary the sampling rate of the digitizer, see External Clock and Reference.

Acquisition Memory

Data from the ADC Closed Analog to Digital Converter is stored in on-board acquisition memory. The amount of memory in use for acquisition can be programmed and is selectable from 1 point to the full amount of acquisition memory available.

Model | Option | Acquisition Memory | Samples/channel
M9203A | -M02 | 256 MB | 64 MS/ch
 | -M10 | 1 GB | 256 MS/ch
 | -M40 | 4 GB | 1 GS/ch

For technical reasons, a certain acquisition memory “overhead” is required for each waveform, reducing the available memory by a small amount.

After acquisition, the raw 12-bit data is subjected to post-calibration processing, which compensates for gain and offset errors in the internal ADCs, The result of this post-processing is then stored and read-out as a 16-bit value. For this reason the returned data will not always be divisible by 16 as may be expected.

Single and Multi-Record Acquisition Modes

Digitizers acquire waveforms in association with triggers. Each waveform is made of a series of measured voltage values (sample points) that are made by the ADC Closed Analog to Digital Converter at a uniform clock rate.

To maximize sampling rates and utilize memory as efficiently as possible the digitizers include both Single and Sequential storage modes. For both of these modes the data of all of the active channels is acquired synchronously; all of the ADC Closed Analog to Digital Converter's are acquiring data at the same time, to within a small fraction of the maximum sampling rate.

The Single Acquisition mode is the normal operation of most digitizer products. In this mode an acquisition consists of a waveform recorded with a single trigger. The user selects the sampling rate and acquisition memory size and sets the number of records to 1 (default value). For details about the trigger sources, see Trigger.

The digitizers also feature a multi-record acquisition mode. This mode allows the capture and storage of consecutive “single” waveforms. Multi-record acquisition mode is useful as it can optimize the digitizer's sampling rate and memory requirements for applications where only portions of the signal being analyzed are important. The mode is extremely useful in almost all impulse-response type applications (RADAR, SONAR, LIDAR, Time-of-Flight, Ultrasonics, Medical and Biomedical Research, etc.).

In multi-record acquisition mode the acquisition memory is divided into a pre-selected number of records. Waveforms are stored in successive memory records as they arrive. Each waveform requires its own individual trigger.

Multi-record acquisition enables successive events, which can occur within a very short time, to be captured and stored without loss. A crucial feature of multi-record acquisition mode is that it has a very fast trigger rearm time. A fast trigger rearm helps produce very low “dead time” between the records of a multi-record acquisition. The “dead time” is the period after the end of an event when the card cannot digitize data for a new trigger event.

Trigger Time Interpolator

The digitizer also measures and stores the arrival time of each trigger using the information from the on board Trigger Time Interpolator (TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time).). This information is essential for determining the precise relation between the trigger and the digitized samples of the signal. The TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time). resolution determines the resolution of the trigger time stamps.

Timebase Range

The timebase range defines the time period over which data is being acquired. For example, the M9203A-M02-SR2 has a standard acquisition memory of 64 MS/ch and maximum sampling rate of 1.6 GS/s (non-interleaved). Therefore, at the maximum sampling rate, the digitizer can record a signal over a time window of up to 41 ms (approx. 67 M points * 625 ps/point).

Combining channels (Interleaving -INT option)

The M9203A digitizer offers the possibility of combining the converters (and their memories) from two channels to analyze a single input channel. With this feature the maximum sampling rate and the maximum amount of acquisition memory can be doubled if all of the input channels are not of immediate interest.

Binary Decimation

A programmable binary decimation may be used to lower the sample rate by a ratio of 2n where n is defined in the range of 1 to 10, depending on the model and configuration (See Table below).

To enable decimation, user should set the sampling rate to required decimated sampling rate.

Aquisition mode | Maximum Decimation Ratio | Lower supported sampling rate
Single record | 210 | 1.5625 MHz
Multi-Record | 25 | 50 MHz

The accuracy of absolute trigger time is guaranteed (as specified in the datasheet) down to sample rates 1/16 of the highest sample rate (1/32 of the highest sample rate with interleaving).


Trigger

The trigger settings applied to the digitizer are used to determine at which time the device will stop acquiring data. The various trigger settings are outlined below.

Trigger Source

The trigger source can be a signal applied to either an Input Channel (internal triggering) or on the TRG IN front panel input connector (external triggering).

The trigger can also be managed through software (Please see AgMD2 API documentation for details).

Trigger Impedance & Coupling

The M9203A has a fixed 50 Ω termination impedance with DC coupling.

Trigger Input Bandwidths

The bandwidth of the channel triggers is from DC to 250 MHz.

The external trigger inputs have a bandwidth from DC to 2 GHz.

Trigger Level

The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger. All trigger circuits have sensitivity levels that must be exceeded in order for reliable triggering to occur.

Both the external trigger input and channel triggers have a hysteresis of 5% of FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. (Full Scale Range).

On external trigger, the Full Scale Range FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. is ±5 V, therefore the digitizer will trigger on signals with a peak-to-peak amplitude > 0.5 V.

When using the channel triggers, the trigger level must be set within Offset ± FSR Closed Full Scale Range:- The span of the voltage input of the Digitizer (negative to positive) including the configured offset voltages. .

Edge Trigger Slope

The trigger slope defines which one of the two possible transitions will be used to initiate the trigger when it passes through the specified trigger level. Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is transitioning from a higher voltage to a lower voltage.

Trigger Time Interpolator

The digitizer also measures and stores the arrival time of each trigger using the information from the on board Trigger Time Interpolator (TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time).). This information is essential for determining the precise relation between the trigger and the digitized samples of the signal. The TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time). resolution determines the resolution of the trigger time stamps.

Please refer to the M9203A datasheet for the relevant specifications.

Trigger precision and resolution

With -SR2 option, the trigger resolution is 6.25 ps (nominal) and the precision 15 ps RMS (nominal) .

The accuracy of absolute trigger time is guaranteed (as specified in the datasheet) down to sample rates 1/16 of the highest sample rate (1/32 of the highest sample rate with interleaving).

Pre- and Post-Trigger Delay

To increase trigger flexibility, a pre- or post-trigger delay can be applied to the trigger position.

The amount of pre-trigger delay can be adjusted between 0 and 100% of the acquisition time window (i.e. sampling interval x number of samples), whereas the post-trigger delay can be adjusted within the time interval:

from 0 to (232 – 1) * block_size (samples)

where block_size is 16 in non-interleaved mode and 32 in interleaved (combined) mode.

Pre- or post-trigger delays are just different aspects of the same trigger positioning parameter:

  • The condition of 100% pre-trigger indicates that all data points are acquired prior to the trigger, i.e. the trigger point is at the end of the acquired waveform.
  • The condition of 0% pre-trigger (which is identical to a post-trigger of 0%) indicates that all data points are acquired immediately after the trigger, i.e. the trigger point is at the beginning of the acquired waveform.
  • The condition of a non-zero post-trigger delay indicates that the data points are acquired after the trigger occurs, at a time that corresponds to the post-trigger delay, i.e. the trigger point is before the acquired waveform.

The digitizer hardware accepts pre- and post-trigger adjustments in increments of 16 samples. By definition post-trigger settings are a positive number and pre-trigger settings are a negative number.

Thus it is only natural that the software drivers treat pre- and post-trigger delays as a single parameter in seconds that can vary between:

– NbrSamples * SamplingInterval (100% pre-trigger)

and +maxPostTrigSamples * SamplingInterval (max post-trigger).


External Clock and Reference

For applications where the user wants to replace the internal clock of the digitizer and drive the ADC Closed Analog to Digital Converter with an external source, either an External Clock or an External Reference signal can be used. The Clock or Reference signals can be entered into the digitizer by the dedicated REF IN and CLK IN connectors.

External Clock (CLK IN)

The External Clock may be used to vary the sampling rate of the digitizer. If selected for the digitizer, it must be continuously present to operate correctly. The input is AC coupled.

Parameter |
 | -SR2
Frequency Range | 1.8 to 3.2 GHz
Resulting sampling rate without interleaving | 900 MS/s to 1.6 GS/s
Resulting sampling rate with interleaving (-INT option) | 1.8 GS/s to 3.2 GS/s
Minimum Amplitude | 0.5 Vpp into 50 Ω
Maximum Power | 15 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P)
Maximum Voltage | ±10 V
Threshold | 0 V

The sampling rate corresponds to half of the external clock frequency in 2-channel mode (non interleaved channels). In interleaved mode (only available with the -INT option), the sampling rate corresponds to the frequency of the external clock signal.

External Reference (REF IN)

For applications that require greater timing precision and long-term stability than is obtainable from the internal clock, a 100 MHz Reference signal can be used.

The External Reference is nominally at 100 MHz. However, frequencies in a range will be accepted. If your input is not at exactly the specified value, you must remember to compensate for the difference in your application since the digitizer and the driver have no way to know about such deviations.

The input is 50 Ω terminated and AC coupled.

Parameter | Value | Tolerance
Nominal Frequency | 100 MHz | ±1 kHz
Signal level | -3 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P) to +3 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P) |
Impedance | 50 Ω |
Coupling | AC |

If synchronization between several digitizers is required, the reference signal should be applied to all of them.


Internal Calibration and Factory Calibration

Internal Calibration

The digitizer includes a high precision voltage source and a 16-bit DAC, used to perform the input voltage and offset calibration.

The software drivers supplied include calibration functions for the timing, gain and offset parameters, which can be executed upon user request. The digitizers are never calibrated in an “automatic” way, (i.e. as a side effect of another operation). This ensures programmers have full control of all calibration operations performed through software in order to maintain proper event synchronization within automated test applications.

For accurate time and voltage measurements it is recommended to perform a calibration once the module has attained a stable operating temperature (usually reached after 20 minutes of digitizer operation after power on). And subsequently a self-calibration should be carried out after any configuration changes are made to the digitizer, before making acquisitions.

A full internal calibration of a digitizer can be time consuming because of the many possible configuration states. Therefore, the self-calibration is performed only for the current configuration state, and is mandatory before making any acquisition. Indeed the MD2 driver prevents an acquisition from being performed unless a self-calibration has first been completed. Note that some configuration changes do not require a new self-calibration. To avoid unnecessary self-calibrations, the Calibration.IsRequired IVI-COM property or the AGMD2_ATTR_CALIBRATION_IS_REQUIRED IVI-C attribute should be queried.

Digitizer can usually work with signals present at the external reference and clock inputs (REF IN and CLK IN). However, to ensure the best performance, or if the calibration is found to be unreliable (as shown by a calibration failure status), it is recommended to remove such signals when working with internal clock.

An application program will shut-down devices at exit. As a consequence, an appropriate warm-up period is expected when starting another application program. In this case, it is recommended to wait for couple of minutes for a stable device temperature, before launching the calibration to ensure full performance.

Smart-calibration

The smart calibration implemented in MD2 driver allows to save time by automatically saving and restoring any self-calibration performed since the beginning of the session. When the acquisition parameters are changed, there is no re-calibration of the instrument if a calibration has already been performed with the same acquisition conditions (i.e. the same set of parameters), except for the clock mode parameters.

Indeed, if the clock mode is changed (i.e. External clock frequency, Clock source or Reference mode paramters), a new self-calibration is systematically required for every acquisition condition with the new clock.

For details How to calibrate the instrument?

Factory Calibration

Whilst the Internal Calibration function will provide a good degree of confidence that your instrument is operating within its specifications on a day-to-day basis, Keysight Technologies recommends that each instrument undergoes a Factory Calibration at least annually to ensure that it remains within the specified performances.

Factory Calibration is the process of measuring the actual performance of an instrument-under-test using lab instruments that in turn have significantly better performance than the instrument-under-test. Lab instrument performance must be traceable to the International System (SI) Units via a national metrology institute (NIST, NPL, NRC, PTB, CENAM, INMETRO, BIPM, etc.)

The measured performance is then compared to published datasheet specifications. For each factory calibration, Keysight Technologies tests the performance corresponding to all datasheet specifications, for every installed option. If needed, the instrument is adjusted and re-qualified before returning it to be in line with full specifications.

For more information, or to request for a calibration please see www.keysight.com/find/calibration.


Trigger Output

When the digitizer is ready to be triggered and a valid trigger signal occurs, a trigger output pulse is generated for external use. This signal is available on the front panel connector, and may be enabled or disabled as required.

The signal is not re-synchronized on the sampling clock but on a sub-multiple of the sampling clock (100MHz).

Figure 2 - Trigger Output Block diagram.

In the default software configuration, the output swing is 1.6 V (±0.8 V) when unloaded and 0.8 V (±0.4 V) when terminated on 50 Ω. The rise and fall times are 2.5 ns typical. The offset can be adjusted, by software control in the range [–2.5 V to +2.5 V] unloaded, or [-1.25 V to +1.25 V] into 50 Ω. The maximum output current capability is ±15 mA. As the output is retro-terminated, it is possible to drive a 50 Ω line un-terminated (HiZ) without loss of performance.

For a TTL compatible signal, set the offset to 1.0 V and the swing at destination will be +0.2 to +1.8 V.

For an ECL compatible signal, terminated on 50 Ω to –1.2 V, set the offset to –1.2 V and the output will be in the range [–0.8 to –1.6 V]).

Alternatively, to reduce the current drawn from the digitizer, the terminations shown here can be used:

Figure 3 - Suggested trigger signal terminations.

The External Trigger Output functionality is implemented in the hardware. No Trigger Out signal occurs for software-generated triggers.


Multi-Purpose Inputs and Outputs

The multi-purpose IO connectors may be used for any of the functions shown in the following table:

IO 3 is reserved for future use.

IO Connector Functions | Type | Description of signal | Notes
Inputs |  |  |
Disabled | - | IO connector is disabled. |
In-ToLogicDevices | - | The Pio_In input signal to the DPU Closed Digital Processing Unit user core (see U5340A FDK Closed FPGA Development Kit manual user core signal description) IO 1-Pio_In(0), IO 2-Pio_In(1) These signals are resynchronized to the sampling clock divided by 16 and transferred from the Control FPGA Closed Field Programmable Gate Array to the DPU Closed Digital Processing Unit with a non-deterministic clock cycle latency. | Used only with the U5340A FPGA Closed Field Programmable Gate Array Development Kit.
Outputs |  |  |
Out-LogicDeviceDPUA | - | The Pio_Out output signal from the DPU Closed Digital Processing Unit user core (see U5340A FDK Closed FPGA Development Kit user manual, user core signal description) IO 1-Pio_Out(0) IO 2-Pio_Out(1) These signals are transferred from the DPU Closed Digital Processing Unit to the Control FPGA Closed Field Programmable Gate Array with a non-deterministic clock cycle latency. | Used only with the U5340A FPGA Closed Field Programmable Gate Array Development Kit.
Out-FPGASyncOut | Pulse | The SyncOut output signal from the DPU Closed Digital Processing Unit user core (see U5340A FDK Closed FPGA Development Kit user manual, core signal description) This signal is transferred from the DPU Closed Digital Processing Unit to the Control FPGA Closed Field Programmable Gate Array with a deterministic clock cycle latency. | Used only with the U5340A FPGA Closed Field Programmable Gate Array Development Kit.
Out-100MHzReferenceClockDivBy2 | Clock | The 100 MHz reference clock divided by 2 (50 MHz) | IO 1 only
Out-SamplingClockDivBy32 | Clock | The sampling clock divided by 32 | IO 1 only
Out-AcquisitionActive | Level | Indicates that the acquisition is currently running. | IO 1 & 2 only
Out-TriggerArmed | Level | Trigger is armed. | IO 1 & 2 only
Out-LowLevel | Level | Fixed 'low' level signal for debug purposes. | IO 1 & 2 only
Out-HighLevel | Level | Fixed 'high' level signal for debug purposes. | IO 1 & 2 only
Out-TriggerAcceptedResync | Pulse | Active when a valid trigger event has occurred. This signal is resynchronized to the sample clock. | IO 1 & 2 only

Signal Logic Levels

The multi-purpose IO signals are 3.3 V CMOS compatible (5V Tolerant buffer). The levels shown in the table below should be observed.

Direction | Low level | High level
Input | <0.8 V | >2.0 to 3.45 V
Output | In the range 0 to 0.8 V | In the range 1.6 to 3.3 V
As an Input

The input is high-impedance and will be pulled high if unconnected via an internal weak pull-up (42.2 k pull-up resistor).

Figure 4 - IO-P schematic

As an Output

The high level output will typically give 1.6 V into 50 Ω. As can be seen in the diagram below, the 3.3 V output buffer has a 50 Ω resistor in series. Therefore the available output high level voltage will depend on the load applied. In the example below a 50 Ω termination will result in a nominal high level of 1.6 V. (Vo = (Rload/(50 + Rload)) * 3.3).


Signal Processing Options

This section describes options which may be used when processing the signal.

Triggered Simultaneous Acquisition and Readout (TSR)

Digital Down-Conversion Mode (DDC / LDC)

Custom Firmware (FDK)


Triggered Simultaneous Acquisition and Readout (TSR)

Overview

The purpose of the TSR option is to acquire in multi-record mode and read the data simultaneously.

This solution allows longer acquisition duration compare with standard DGT and is dedicated to applications requiring no trigger loss.

TSR option is not supported in association with average (AVG) or peak detection (PKD) mode.

Functional Description

Standard Acquisition vs. TSR Acquisition

The following pictures illustrate the differences between a standard acquisition and a TSR acquisition.

In a Standard Acquisition and Readout the duration of the acquisition is limited by the digitizer internal buffer memory size. The readout of the data is performed after the acquisition has stopped. The acquisition data rate supported is up to the maximum allowed by the digitizer.

In a Triggered Simultaneous Acquisition and Readout, the readout of the data is performed during the acquisition. The readout can be performed as soon as a programmable number of records is acquired.

Each segment is triggered by an external or software trigger. Unlike CSR mode, this mode allows gaps in the acquisition.

After initiating the acquisition, when the 1st trigger occurs, the instrument records data and stores it into a circular buffer which can be read simultaneously.

Thanks to TSR mode, the data rate can be sustained without losing any trigger. The maximum performances of the system depend on the records size and trigger rate of the application.

Mode of Operation

TSR option implements an optimal and automated control of memory addressing. It results in an easy to use solution when compared with solutions requiring memory bank management.

User does not need to select the number of records. The driver provided with the digitizer will automatically select the maximum number of records depending on the memory option and the number of samples per records.

If the TSR Enabled property is set to true (and the Initiate Acquisition function is launched), the instrument will acquire data and store them into a circular buffer which can be read simultaneously.

Once the Acquisition is initiated, the user has to poll on the TSR IsAcquisitionComplete property to check for the availability of data. When minimum programmable number of records are acquired, data can be fetched through standard (single- or multi-record) fetch functions.

The TSR Continue function can be called to release the buffer containing the read data and make it available for the next acquisitions. User can also release the buffer without reading any or all the data.

The TSR MemoryOverflowOccurred property indicates that no more memory is available to perform additional acquisitions, implying that follow-on triggers may be lost.

For maximum performance, it is recommended to optimize the number of record to be acquired before the readout starts (NumRecordsToAcquire). Typically, if the number of samples per record is low, reading several records in one single Direct Memory Access (DMA) optimize the DMA transfer. There is a compromise between memory readout frequency and PCIe delay.(Recommendation is to set the number of record before readout to reach around 1MB of data).

It is recommended to set the NumRecordsToAcquire to a value close to 1MB/(Record size).

If an overflow occurs, the writing is disabled, implying that follow-on triggers may be lost. A property indicates that no more memory is available to perform additional acquisitions. The already acquired data are still valid and can be read-out. Memory can be cleared only with Acquisition -> Abort()

A typical usage example is shown below (pseudo-instructions):

Enable TSR operation

Initiate acquisition

Loop until needed

Check for memory overflow

Poll for acquisition completion

Fetch data

Continue (release memory)

End loop

Abort acquisition

A complete C++ example for TSR features can be found in the directory:

<IVIROOTDIR>\Drivers\AgMD2\Examples\Visual Studio\Cpp\Cpp_TSR

Due to design constraints, the number of trigger events needed to have an acquisition complete can be higher than the number of records configured (through NumRecordsToAcquire property). It is therefore mandatory to query the TSR IsAcquisitionComplete property to check for data availability.

TSR Configuration

The interfaces/methods/properties (functions/attributes) listed below are provided by the Keysight MD2 driver. Detailed help may be found in the AgMD2 IVI Driver Reference Manual.

IVI-COM

Interface | Method / Property name
IAgMD2Acquisition2TSR | Continue
IAgMD2Acquisition2TSR | Enabled <p>
IAgMD2Acquisition2TSR | IsAcquisitionComplete <p>
IAgMD2Acquisition2TSR | MemoryOverflowOccurred <p>

IVI-C

Functions

AgMD2_TSRContinue

Attributes

AGMD2_ATTR_TSR_ENABLED

AGMD2_ATTR_TSR_IS_ACQUISITION_COMPLETE

AGMD2_ATTR_TSR_MEMORY_OVERFLOW_OCCURRED


Digital Down-Conversion mode (-DDC)

This function is only available on the M9203A Digitizer with the -DDC option.

Principle of operation

The digital down converter (DDC) mode of the digitizer allows to convert a digitized real signal centered at a center frequency (Fc) to a baseband complex signal. In addition to down conversion, DDC decimates to a lower sampling rate, allowing follow-on signal processing by lower speed processors.

The M9203A offers 2 independent channels of down-conversion, each channel accepting data at rates up to , and down converts the data to lower rates at arbitrary center frequencies.

Figure 1. Digital Down Conversion functional block diagram.

Digital down conversion algorithms within the digitizer allow for the translation of the digitized IF to a complex-valued (I/Q) baseband output allowing analysis of narrowband signals. Filtering can be invoked to increase accuracy at reduced bandwidth and sample rates.

For example, acquiring a narrow band radio signal with a 1 Hz resolution on the sidebands would require capturing 1 second of data. At the sample rate of the M9203A (1.6 GS/s) this would require massive amounts of memory, and a very large FFT. However, using the DDC function reduces the sample rate, for instance to 1.56 MS/s. With DDC, user only need to acquire 1/1000th of the data, making the measurement possible, and providing a much more reasonably sized FFT.

Reducing the bandwidth with a corresponding decrease in sample rate is a fundamental function of DDC. When the bandwidth of the ADC Closed Analog to Digital Converter data is reduced, both quantization noise and unwanted signals are removed from the sample stream. Reducing bandwidth also increases the effective number of bits (ENOB Closed Effective Number Of Bits - expresses the quality of the ADC Closed Analog to Digital Converter quantification.). The design ensures that the ENOB Closed Effective Number Of Bits - expresses the quality of the ADC Closed Analog to Digital Converter quantification. at the minimum decimated bandwidth is sufficient to capture all data.

The decimation filters are state-synchronized across all channels, this maintains a time alignment across channels as well as ensuring a common LO phase across all DDCs.

Features:

  • 2 channels support
  • Two digital down converter per DPU Closed Digital Processing Unit
  • Independent Local Oscillator (LO) per DDC channel
  • Phase coherent acquisition and processing across all DDC channels: assures that signals have a constant phase difference at same frequency.
  • Supported trigger modes:

    1. Software trigger

    2. Channel signal trigger

    3. External signal trigger

    4. DDC output magnitude trigger (digital trigger)

  • External clock support.
  • External reference supported
  • Support Triggered Multi-records

DDC option differs from the digital down converter offered with CBx options, for details Difference between digital down converter in DDC and CBx options.

Process in frequency domain

When a signal is acquired by a digitizer, aliased images appear at frequencies depending on sampling rate frequency (Fs) due to sampling and folding-back (See example in figure below). The aliased signal in 1st Nyquist zone is used for down-conversion and translated in baseband thanks to Local Oscillator (LO) at configurable center frequency (Fc). Then, digital Low-Pass Filtering (LPF) is used to remove some unwanted aliased signal. The baseband signal is decimated then used for streaming and recording.

Figure 5 - Example of acquisition of a signal in 3rd Nyquist zone: Sampling causes initial signal in Instantaneous Bandwidth (IBW Closed Instantaneous Bandwidth) to be aliased–back in 1st Nyquist zone. Then, using LO at Fc, the resulting baseband signal is used for streaming.

Usage and guidelines

Filtering of input signal (anti-aliasing)

At sampling, unwanted signal in other Nyquist bands can creates unexpected aliased signals in the working bandwidth. This could deteriorate the signal once translated in baseband.

In order to eliminate the chance of aliasing, depending on the Nyquist band used, it is recommended to reduce the input signal bandwidth with low-pass or a band-pass filter at the digitizer input. Its bandwidth value should select the signal of interest.

This filter would generally be at Fs/2, in the case of the M9203A that is 800 MHz for SR2 option. More specifically, a filter with pass-band (A)Fs and stop-band (1-A)Fs, with A typically being 0.4, which would provide an alias protected bandwidth of A*Fs. Of course this may not be necessary where the input signal is already narrow-band. Signal conditioning should also scale the signal peak to close to the full-scale value (within 2 dBm Closed Power measurement relative to 1 mW, P (dBm) = 10log10(1000.P)) at the digitizer input for optimum performance.

Local Oscillator (Center Frequency)

Digital Down Conversion (DDC) is performed at an Fc center frequency which is configurable by the user across the entire bandwidth of the digitizer, and with a resolution of 0.01 Hz (with SR2 option), providing very flexible tuning capabilities.

On the -F05 option model, setting the LO frequency above the maximum analog bandwidth of 650 MHz is not permitted. Similarly, with the -F10 option, if the BW limiter is selected, the LO frequency should not be placed above 650 MHz.

Instantaneous Bandwidth and Nyquist zones consideration

Due to aliasing, the Instantaneous analysis Bandwidth (IBW Closed Instantaneous Bandwidth) of input signal must not overlap on two Nyquist zones —Nyquist zones are limited by frequencies multiples of Fs/2 (See figure below).

Figure 6 - The acquired input signal must not overlap on two Nyquist band.

If necessary, the IBW Closed Instantaneous Bandwidth can be moved inside a Nyquist Zone by translating the signal and Fc thanks to an analog down converter such as the M9362AD01 quad down converter.

Re-arm Time

The re-arm time is defined as the time required after the completion of a data acquisition record and before a new triggered acquisition record can be accepted. The re-arm time for the DDC firmware is about 2 us across the entire selectable DDC bandwidth.

The following picture illustrates graphically the re-arm time concept. Each triggered acquisition lasts for a given amount of samples. Only after the re-arm time has completed, can a new trigger can be accepted and a new recordacquired.

Figure 7 - DDC Re-arm Time

Decimation, Sampling Frequency & Bandwidth

Decimated sampling rate is selectable by user. User can choose the lowest decimated sampling rate corresponding to the Instantaneous Analysis Bandwidth (IBW Closed Instantaneous Bandwidth) required for its application (See Table below). The specified IBW Closed Instantaneous Bandwidth is guaranteed to be free from alias products (attenuated by at least 80 dB).

The decimation is defined by the Decimation Ratio (or Decimation Numerator).

The resulting Decimated sampling rate, after decimation is given by:

The maximum analysis bandwidth depends on the sampling rate option (-SR2) of your M9203A, and also on the -DDC/-LDC option which has been purchased. There is a full performance DDC option (-DDC) as well as a more cost-effective limited DDC option (-LDC).

The decimated sampling rate control also controls the bandwidth. These rates differ depending on the model option, and are shown in the table below. Note that the intermediate steps can be calculated using the formulas shown in the penultimate row.

n | Decimation ratio | Decimated Sampling Rate [MS/s] | Instantaneous Analysis Bandwidth (IBW Closed Instantaneous Bandwidth) [MHz] | Maximum Acquisition Memory Time [s]
2 | 4 | 400 | 320 | 1.342
3 | 8 | 200 | 160 | 1.342
4 | 16 | 100 | 80 | 2.684
5 | 32 | 50 | 40 | 5.368
6 | 64 | 25 | 20 | 10.736
7 | 128 | 12.5 | 10 | 21.472
8 | 256 | 6.5 | 2 | 42.949
... | ... | (100/2n-4)* | (80/2n-4)* | 42.949
19 | 524288 | 0.305 kS/s | 244 kHz | 42.949

* with n>=2.

The results presented in this table are achieved with the -M16 option.

Data Scaling

In processing the signal the negative spectrum component is filtered out by the down-converter. Therefore due to this filtering process the power level of the signal brought into baseband represents only half of the original (pre-DDC) signal power.

Same applies to signal amplitude. A 'Data scaling' option is available, whereby a factor of two is applied to the amplitude, and the down-converted signal is returned to the true input amplitude level. When is used, the user is operating with the same convention as 89600 VSA Software. Note that if the center frequency (Fc) is set to '0', this factor is not applied.

DDC Magnitude Trigger

When in DDC mode an additional trigger is available: 'Magnitude Trigger', corresponding to a digital trigger function of DDC output magnitude.

The magnitude trigger circuit calculates the magnitude of the real and imaginary parts by the following equation:

Triggering is performed by comparison with a level and a hysteresis value. The hysteresis value may be used to avoid triggering on noise signals. i.e. A rising edge trigger will occur when the signal reaches the level value, having passed through level - hysteresis. Conversely for a falling edge, the trigger will occur at level having fallen through level + hysteresis.

Dwell Time

The potential trigger is further qualified by a dwell time which is specified in samples. Positive values of dwell indicate the number of samples that must be in the initial trigger state (e.g. below the low threshold for a rising edge trigger) before a trigger will be recognized. Negative values of dwell indicate the negative of the dwell time, which is the number of samples that must be in the second trigger state before a trigger is recognized.

It is easiest to explain the use of these values by several examples. Suppose the input signal is some kind of burst transmission, such as a TDMA signal consisting of a burst of signal with silence between the bursts. Note that even though in general the magnitude of the burst signal may be above our threshold, there can be samples in the middle of the burst whose magnitude is below our threshold. If we just used a rising edge trigger to try to capture the start of a burst, we might get false triggers if we happened to arm our trigger in the middle of a burst. In that case we might trigger later in the middle of the burst if any sample fell below our threshold. To guarantee triggering on the start of the burst, we might say that we won't trigger until 20 consecutive samples are below the threshold (to detect the gap between bursts) and then trigger the next time a sample goes above the threshold. We would set this up by using a positive slope (slope=0) and a dwell value of +20. Then we would only trigger after the signal has been below the threshold for at least 20 samples and then rises above it.

Suppose we want to trigger on the end of the burst instead of the beginning. Then we would want to use a negative slope (slope=1) and a negative dwell value. If we set slope=1 and dwell = -20, then we would trigger only if the signal goes above the threshold (indicating that a burst is in progress) and then goes below the threshold for 20 consecutive samples (indicating the gap between bursts). Without the dwell time, we might erroneously trigger if a sample in the middle of the burst fell below the threshold.

Data Readout

Data correspond to complex signal = REAL + j IMAGINARY = I (n bits) + jQ (n bits).

In order to optimize data transfers at the top sampling rate, a different data type is used compared to the lower sampling rates.

16-bit I/Q mode

For maximum decimated sampling rate (n = 2):

Output data are packed on 32 bits (I–16 bits, Q–16 bits)

32-bit I/Q mode

For other decimated sampling rates (n > 2):

Output data are packed on 64 bits (I–32 bits, Q–32 bits)

Driver methods

The following applies:

  • DDCCoreFetchWaveformInt16 is supported for the highest sample rate only.
  • DDCCoreFetchWaveformInt32 supported for all except the highest sample rate.

For these methods, the parameter ActualPoints is given in number of I-Q data point pairs, or complex samples. For the DDCCoreFetch methods, the units of the OffsetWithinRecord and NumPointsPerRecord parameters are also complex samples. The FirstValidPoint parameter, which is primarily intended for dealing with memory alignment, is always given in array elements, like the WaveformArraySize parameter.

Digital Down Conversion (DDC) Configuration

Configuration & Control

The M9203A Digitizer DDC operation is configured and controlled using the IviDigitizer class. The methods listed below are provided by the Keysight MD2 driver. Detailed help on these interfaces may be found in the separate help file.

Each DDC core corresponds to a channel (DDCCorei for channeli)

The decimation ratio is defined by the Decimation Numerator (the Decimation Denominator is currently fixed to 1).

The Decimation Numeratorshould be the same for each DDC Core.

The Center Frequency defines the frequency (in MHz) that will be used for the local oscillator and could be chosen independently for each DDC Core.

Driver | Functions / Methods / Interface | Attributes / Properties | Detailed help located
IVI-COM | IAgMD2DDCCore | CenterFrequency, DataSource, DecimationDenominator, DecimationNumerator, LOInitialPhase | MD2 IVI Driver Help
 | IAgMD2DDCCore.FetchWaveformInt16 |
 | IAgMD2DDCCore.FetchWaveformInt32 |
 | IAgMD2TriggerSourceMagnitude | DwellTimeSamples, Slope
IVI-C | AgMD2DDCCore | AGMD2_ATTR_DDCCORE_CENTER_FREQUENCY AGMD2_ATTR_DDCCORE_COUNT AGMD2_ATTR_DDCCORE_DATA_SOURCE AGMD2_ATTR_DDCCORE_DECIMATION_DENOMINATOR AGMD2_ATTR_DDCCORE_DECIMATION_NUMERATOR AGMD2_ATTR_DDCCORE_LO_INITIAL_PHASE
 | AgMD2_DDCCoreFetchWaveformInt16 |
 | AgMD2_DDCCoreFetchWaveformInt32 |
 | AgMD2_GetDDCCoreName |
 | AgMD2_TriggerMagnitudeConfigure | AGMD2_ATTR_TRIGGER_MAGNITUDE_DWELL_TIME_SAMPLES AGMD2_ATTR_TRIGGER_MAGNITUDE_SLOPE

To enable and use DDC mode through the SFP Closed Soft Front Panel application, please refer to the MD2 SFP Help .

Code example

A code examples are available, in following directories:

Example for IVI-C:

Or the alternative drive letter where the Keysight MD2 Driver has been installed on your machine. C :\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\CppIviC\CPP_IVIC_DDC

Example in C-sharp:

Or the alternative drive letter where the Keysight MD2 Driver has been installed on your machine. C :\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\CSharp\CS_DDC

Difference between digital down converter in DDC and CBx options

The digital down converter functionality offered with the -DDC option has not the same set of features than the one coming with -CB1/CB2 options. Main differences are:

Function description | CB1/CB2_DDC | DDC
Control through API | No | Yes
Control through command line application (executable file) | Yes | No
VSA 89600 | No | Yes
Magnitude trigger | No | Yes
Multi-record | No | Yes
Decimation steps | 6 | 17
Crossbar switch (allowing 2 DDC cores on a single physical channel) | Yes | No
12-bit mode (data throughput optimization) | Yes | No
Streaming & recording | Yes | No


Custom firmware capability (FPGA Development Kit)

The -FDK Closed FPGA Development Kit (FPGA Closed Field Programmable Gate Array Development Kit) option allows the access to the four on-board processing FPGAs for custom algorithm implementation.

The U5340A FPGA Closed Field Programmable Gate Array development kit can be used for implementing such algorithm for deployment on embedded systems using a HDL design entry approach.

For details, please refer top U5340A FDK Closed FPGA Development Kit product www.keysight.com/find/U5340A and U5340A FDK Closed FPGA Development Kit User Manual.


Application Options

This section describes specific applications options.

High Fidelity Digitizer (BB1)

Digitizer Streaming (CB0)

Digital Down-Converter Streaming (CB1/CB2)


High Fidelity Digitizer (BB1)

This option provides enhanced performances:

  • by compensating the ADC Closed Analog to Digital Converter and front-end distortion,
  • by minimizing interleave spurs, and
  • by reducing the overall noise bandwidth.

It allows the following usages as high fidelity baseband digitizer:

  • 1.6 GS/s with 650 MHz bandwidth, up to 64 MSamples/ch.
  • 800 MS/s with 400 MHz bandwidth, up to 32 MSamples/ch.
  • 400 MS/s with 200 MHz bandwidth, up to 16 MSamples/ch.
  • 200 MS/s with 100 MHz bandwidth, up to 8 MSamples/ch.
  • 100 MS/s with 50 MHz bandwidth, up to 4 MSamples/ch.

This option is not field-upgradable.

BB1 option usage

M9203A-BB1 digitizer (without -DGT mode)

When running acquisitions, the high-fidelity mode is enabled by default (named BaseBand0 mode in driver, see Table below).

Depending on the application, the bandwidth can be reduced by decreasing the sampling rate according to the list above (using AGMD2_ATTR_SAMPLE_RATE IVI-COM attribute or IAgMD2Acquisition.SampleRate IVI-C property).

Special consideration for M9203A digitizer supporting both -BB1 and -DGT options

Default

If both high fidelity -BB1 and standard digitizer -DGT modes are supported by your digitizer, then the default mode is standard digitizer DGT.

Enabling high fidelity -BB1 mode

The high fidelity -BB1 mode requires the BaseBand0 mode to be enabled in driver: using AgMD2AcquisitionModeBaseBand0 for IVI-COM driver or AGMD2_VAL_ACQUISITION_MODE_BASE_BAND0 for IVI-C driver (See Table below).

Driver | Attributes / Enumeration | Value | Comment | Detailed help location
IVI-COM | AgMD2AcquisitionModeEnum | AgMD2AcquisitionModeBaseBand0 AgMD2AcquisitionModeNormal | Enable high fidelity BB1 mode Enable standard digitizer DGT mode | MD2 IVI Driver Help
IVI-C | AGMD2_ATTR_ACQUISITION_MODE | AGMD2_VAL_ACQUISITION_MODE_BASE_BAND0 AGMD2_VAL_ACQUISITION_MODE_NORMAL | Enable high fidelity BB1 mode Enable standard digitizer DGT mode

When switching from BB1 high-fidelity mode (BaseBand0 mode) to standard digitizer DGT mode (Normal mode), user should disable the BaseBand0 mode.

For users with a M9203A -DGT, -BB1, -F10 (full bandwidth), please note that BB1 high-fidelity mode is dedicated and qualified only for limited bandwidth (650 MHz). Thus if you run an acquisition in standard DGT mode with full bandwidth, then want to switch to BB1 high-fidelity mode (BaseBand0 mode), you have to:
- Enable the bandwidth limiter filter (BWL) (using IAgMD2ChannelFilter.Bypass IVI-COM property or the AGMD2_ATTR_INPUT_FILTER_BYPASS IVI-C attribute).
- Enable the BaseBand0 mode (See above table).

Then, if you want to switch back to standard DGT mode with full bandwidth, you have to:
- Disable the BaseBand0 mode, by enabling standard digitizer mode.
- Disable the bandwidth limiter filter (BWL).

(This BWL requirement doesn't affect M9203A -DGT, -BB1, -F05 digitizer).


Digitizer Streaming (CB0)

CB0 is a turnkey reference bundle, based on the continuous simultaneous acquisition and readout architecture, implementing a real time digitizer data recorder for gapless acquisition. It includes a command line application and an easy to use data viewer application is also provided.

  • This digitizer streaming and recording option with bundled applications provides:
  • Guaranteed recording specification in a specific qualified system (Please refer to datasheet)
  • Various recording speed controlled by application
  • Adaptable sampling rate (decimation and external clock)
  • Data throughput optimization (12-bit, 10-bit or 8-bit mode).

This option is using a M9203A pre-configured version composed:

  • 2 channels version (-CH2)
  • 1.6 GS/s sampling rate (-SR2)
  • Full bandwidth (-F10)
  • 4 GB acquisition memory (-M40)
  • Digitizer firmware (-DGT)

For documentation relative to this option, please refer to CB0_DGT_streaming_Help.chm installed from your Keysight High Speed Digitizer Application DVD or use following path:

<C: or your installation drive letter>\Program Files\Keysight\High-Speed Digitizers Applications\Help\CB0_DGT_streaming_Help.chm


Digital Down-Converter Streaming (CB2)

This bundle enables continuous gapless acquisition, implementing:

  • Digital down converter functionality in real time
  • Data steaming to host
  • Multichannel recording to disk all I/Q samples for later analysis.
  • Independent local-oscillators, with phase-coherency between channels.

This option provides:

  • Guaranteed recording specification up to 320 MHz instantaneous bandwidth (IBW Closed Instantaneous Bandwidth) with tunable intermediate frequency with recommended configuration.
  • Data throughput optimization (I/Q samples with 32-bit, 16-bit or 12-bit mode).

This option is using a M9203A pre-configured version:

M9203A
CB2

1.6 GS/s sampling rate (-SR2)
2 channels version (-CH2)
Full bandwidth (-F10)

4 GB acquisition memory (-M40), 2 GB/ch
SX315T DPU Closed Digital Processing Unit FPGA Closed Field Programmable Gate Array (-SX3)
Digitizer firmware (-DGT)

The included digitizer data streamer is an intuitive command line application which allows to control the M9203A and to adapt its data rate to the target application.

A data viewer is provided as a simple graphical user interface (GUI) which allows to read, display, select and export the data stored.

For documentation relative to this option, please refer to CB_DDC-streaming_Help.chm installed from your Keysight High Speed Digitizer Application DVD or use following path:

<C: or your installation drive letter>\Program Files\Keysight\High-Speed Digitizers Applications\Help\CB_DDC-streaming_Help.chm


Electrical & Environmental Specifications

For full specifications, please refer to the product data sheet which may be found on the CD which came with your product, or from the Keysight Technologies website: www.keysight.com/find/M9203A


Programming Information

This section provides general programming advice and specific information regarding the use of the Keysight drivers.

The AgMD2 IVI driver provides access to the functionality of AgMD2 digitizers through a COM server or ANSI C API which also complies with the IVI specifications.

The AgMD2 API documentation can be found MD2 IVI Driver Help in or from Start > All programs > Keysight Instrument Drivers > IVI-COM-C Drivers > AgMD2 Digitizer > AgMD2 IVI Driver Help

Program examples can be found in Start > All programs > Keysight Instrument Drivers > IVI-COM-C Drivers > AgMD2 Digitizer > AgMD2 Example Programs

IVI-COM Driver development environments

The AgMD2 IVI-COM driver can be used in the following development environments:

  • Visual C#
  • Visual C++
  • Visual Basic.NET
  • Keysight VEE Pro
  • LabVIEW
  • MATLAB.

The section AgMD2 IVI-COM Driver > Programming with the IVI-COM Driver in Various ADEs of the AgMD2 IVI documentation describes how to use the IVI-COM driver from the different development environments.

Additionally AgMD2 IVI-COM sample codes can be found in the folders:

  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\CppIviCom
  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\CSharp
  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\MATLAB\IVI-COM
  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\VisualBasic

IVI-C Driver development environments

The AgMD2 IVI-C driver can be used in the following development environments:

  • Visual C++
  • LabWindow/CVI
  • LabVIEW
  • MATLAB.

The section AgMD2 IVI-C Driver > Programming with the IVI-C Driver in Various ADEs of the AgMD2 IVI documentation describes how to use the IVI-C driver from the different development environments.

Additionally AgMD2 IVI-C sample codes can be found in the folder:

  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\CppIviC
  • C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Examples\MATLAB\IVI-COM

Section Content

Initial Configuration

How To ...

ApplySetup

Known issues for MATLAB users


Initial Configuration

At initialization, the driver uses the pre-defined defaults values. The following table details the initial configuration of the digitizer.

Property | Default value | Comment
Channeli | Enable |
Input filter | For -F10 Bypass = Yes | Not relevant for -F05, no filter available.
Vertical range | 2 (Volts) |
Vertical offset | 0 (Volts) |
Vertical coupling | DC |
Trigger source | Internal1 |
Trigger delay | 0 (ns) |
Trigger type | Edge |
Trigger coupling | DC |
Trigger level | 0 (Volts) |
Trigger slope | Positive |
Interleave | Disable |
Mode | Normal (DGT) |
Sampling rate | Depends on SRx option | Default is the higher value supported by the module without interleaving
Sample clock | Internal |
Sample clock external frequency | Depends on SRx option | External Clock and Reference
Sample clock external divider | Depends on SRx option | Fixed (Sample clock external frequency / Sampling rate)
Reference oscillator | Internal |
Reference oscillator frequency | 100 MHz | Fixed
Record size | 1024 |
Number of records to acquire | 1 |


How To ...

Discover the PXI Instrument

Calibrate the instrument

Access repeated capabilities

Generate a software trigger

Perform interleaved acquisition

Bypass the filter

Binary decimation (depending on firmware)

Perform partial readout

Load a new firmware

Migrate from Acqiris or MD1 to MD2


Discover the PXI Instrumen

You are here: M9203A User Manual > Programming Information > How To ... > Discover the PXI Instrument

How to discover the PXI Instrument?

The C/C++ code below can be used to discover the PXI instruments on user system and get their VISA addresses.

#include <stdio.h>

#include <visa.h>

int main()

{

ViSession rm = VI_NULL;

ViSession vi = VI_NULL;

viOpenDefaultRM( &rm );

ViChar search[] = "PXI?*::INSTR";

ViFindList find = VI_NULL;

ViUInt32 count = 0;

ViChar rsrc[256];

ViChar modelName[256];

ViStatus status = viFindRsrc( rm, search, &find, &count, rsrc );

if ( status==VI_SUCCESS && count>0 )

{

do

{

viOpen(rm, rsrc, 0, 0, &vi);

viGetAttribute(vi, VI_ATTR_MODEL_NAME, modelName);

viClose(vi);

printf( "Found: \"%s\" - Model Name: %s\n", rsrc, modelName);

status = viFindNext( find, rsrc );

} while( status==VI_SUCCESS );

viClose( find );

}

viClose( rm );

}


How to calibrate the instrument?

Calibration principle

The card is initialized without calibration.

A calibration is mandatory before making any acquisition to guarantee measurement accuracy. MD2 driver prevents an acquisition from being performed unless a self-calibration has first been completed.

Since a full internal calibration of a digitizer can be time consuming because of the many possible configuration states, the self-calibration is performed only for the current configuration state. A new self-calibration is required after every change of configuration of the instrument.

Internal Calibration and Factory Calibration

Running fast calibration

The function SelfCalibrate should be used to perform a fast calibration.

As explained above, a calibration is required after every acquisition parameter modification (e. g. full scale range, filter, sample rate, ...). The Calibration.IsRequired IVI-COM property or the AGMD2_ATTR_CALIBRATION_IS_REQUIRED IVI-C attribute can be used to check if a new self calibration is required .

MD2 Smart-calibration

The smart calibration implemented in MD2 driver allows to save time by automatically saving and restoring any self-calibration performed since the beginning of the session. When the acquisition parameters are changed, there is no re-calibration of the instrument if a calibration has already been performed with the same acquisition conditions (i.e. the same set of parameters), except for the clock mode parameters.

Indeed, if the clock mode is changed (i.e. External clock frequency, Clock source or Reference mode paramters), a new self-calibration is systematically required for every acquisition condition with the new clock.

Parameter change requiring a new self calibration

The table below lists the parameters that require a new self calibration of the instrument when changed.

 | Parameter | Calibration required
Acquisition | Sampling rate | Only the 1st time, for an identicalset of parameter values.
Channel1 parameters | Vertical range
 | Input filter Bypass (Yes/No)
 | Interleave (Enable or not)
Channel(i) parameters | Vertical range
 | Input filter Bypass (Yes/No)
 | Interleave (Enable or not)
Trigger | Trigger source | Only the 1st time
Clock mode | External clock frequency | Each time this parameter changes
 | Clock source | Each time this parameter changes
 | Reference mode (External or Internal Reference) | Each time this parameter changes

The channel parameters are calibrated independently per channel.

Saving and restoring calibration setup

It is also possible to save calibration parameters and restore them during future sessions.

The function Calibration SaveToFile allows to save in a single file the calibration values from all calibrations done in the current user session (IVI-COM method: IAgMD2Calibration.SaveToFile, IVI-C function: AgMD2_CalibrationSaveToFile).

In the next session, after performing a single calibration, user can restore all the saved calibration values using Calibration Load From File function (IVI-COM method: IAgMD2Calibration.LoadFromFile, IVI-C function: AgMD2_CalibrationLoadFromFile).

To guarantee acquisition accuracy, at least one calibration with the chosen clock mode and trigger source (group B and C) has to be performed when starting a new session.Thus the Save and Load functions, only apply to Acquisition sampling rate and Channel parameters (group A). Only these parameters can be re-used between sessions.

Save and restore procedure

User can generate a set of calibration values and store the calibrated configurations:

  1. Open a session to the module and put it into operating conditions
  2. Calibrate the module in all desired configurations
  3. Call Calibration SaveToFile to store the calibration state of all calibrated configurations
  4. Close the module session.

Then the previously saved calibration states could be re-used:

  • Open a session to the module
  • Configure required the clocking mode and trigger source (internal sample clock / external sample clock / external reference oscillator)
  • Call SelfCalibrate once for each trigger source user intends to use
  • Call Calibration LoadFromFile to restore the previously saved calibration state
  • The calibration state loaded from the file which best matches the current configuration and temperature will be used for acquisitions

If the clock mode (Reference Oscillator Source or Sample Clock Source) is changed, steps 3 and 4 have to be repeated.


How to access repeated capabilities ?

For M9203A, the AgMD2 driver supports the following repeated capabilities with pre-defined values detailed in following table.

Repeated capability | Available instance name
Channel | "Channel1", "Channel2"
TriggerSource | "Internal1", "Internal2", "External1", "Software", "Immediate",
ArmSource | Not supported
LogicDevice | For -FDK Closed FPGA Development Kit option only: "DPUA"
PrivateFirmware | Not accessible
PrivateStore | Not accessible
ControlIO1 | "ControlIO1", "ControlIO2", "ControlIO3"
DelayControl | Not supported
LogicDeviceIFDL (Inter FPGA Closed Field Programmable Gate Array Data Link) | Not supported
LogicDeviceMemoryBank | For -FDK Closed FPGA Development Kit option only: "DPUA:DDR3A", "DPUA:DDR3B"
MonitoringValue | These parameters are for information only or can be used for debugging purpose. The are accessible through the MD2 SFP Closed Soft Front Panel or the command below. For details, please refer to MD2 IVI Driver Help.
Stream | Not supported

1For details, please refer to Multi-Purpose Inputs and Outputs.

The number of instances and their names however can be queried from the driver:

  • Using the AgMD2 IVI-COM driver:

    Collection interfaces have a Count property, and a Name[index] array.

  • Using the AgMD2 IVI-C driver:

    For each repeated capability Xxx, there is a AGMD2_ATTR_XXX_COUNT attribute and a AgMD2_GetXxxName function (e.g. AGMD2_ATTR_CHANNEL_COUNT attribute and AgMD2_GetChannelName function).


Migrate from Acqiris or MD1 to MD2

You are here: M9203A User Manual > Programming Information > How To ... > Generate a software trigger

How to generate a software trigger?

The function AgMD2_SendSoftwareTrigger sends a single software trigger and needs to be called as many times as they are incomplete records.


Perform interleaved acquisition

You are here: M9203A User Manual > Programming Information > How To ... > Perform interleaved acquisition

How to perform time-interleaving acquisitions?

It is possible to combine two channels and to perform an acquisition at higher sampling rate.

The following example give the function calls used to:

  • combine the two channels,
  • use channel 1
  • and set the sampling rate to GS/s

Channels time-interleaving (IVI-COM)

IAgMD2ChannelPtr spCh1 = spDriver->Channels->Item[L"Channel1"];

spCh1->TimeInterleavedChannelList = "Channel2";

double sampleRate = e9;

spDriver->Acquisition->SampleRate = sampleRate;

Channels time-interleaving (IVI-C)

AgMD2_SetAttributeViString(session, "Channel1", AGMD2_ATTR_TIME_INTERLEAVED_CHANNEL_LIST, "Channel2");

AgMD2_SetAttributeViReal64(session, "", AGMD2_ATTR_SAMPLE_RATE, e9);


How to enable or bypass the filter?

The following commands allow to bypass the filter.

  • Using the AgMD2 IVI-C driver:

AgMD2_SetAttributeViBoolean(session, "Channel1", AGMD2_ATTR_INPUT_FILTER_BYPASS, VI_TRUE);
  • Using the AgMD2 IVI-COM driver:

IAgMD2ChannelPtr spCh1 = spDriver->Channels->Item[L"Channel1"];

spCh1->Filter->Bypass = true;

The following commands allow to enable the filter.

  • Using the AgMD2 IVI-C driver:

AgMD2_SetAttributeViBoolean(session, "Channel1", AGMD2_ATTR_INPUT_FILTER_BYPASS, VI_FALSE);
  • Using the AgMD2 IVI-COM driver:

IAgMD2ChannelPtr spCh1 = spDriver->Channels->Item[L"Channel1"];

spCh1->Filter->Bypass = false;


How to do binary decimation ? (depending on firmware)

The binary decimation is not supported for all combinations of firmware, channel configuration and sampling rate.

It is supported only with the digitizer (-DGT) or TSR (-TSR) mode. It is not supported in Averager (-AVG) or Peak Detection (-PKD) mode.

The available decimation factors depend on the channel configuration (-CHx) and sampling rate (-SRx) options of your digitizer.

Please refer to the Data Acquisition Section for more information.

  • Using the AgMD2 IVI-COM driver:

To use the binary decimation and set the sample rate to a lower value use the SampleRate property.

sampleRate = 200e6;

spDriver->Acquisition2->SampleRate = sampleRate;

  • Using the AgMD2 IVI-C driver:

To use the binary decimation and set the sample rate to a lower value use the AGMD2_ATTR_SAMPLE_RATE attribute.

sampleRate = 200e6;

status=AgMD2_SetAttributeViReal64(session,””, AGMD2_ATTR_SAMPLE_RATE,sampleRate);


Perform partial readout

You are here: M9203A User Manual > Programming Information > How To ... > Perform partial readout

How to perform partial readout?

If the acquisition uses a single record with large record size, the digitizer memory can be read in two or more blocks. It is possible to read the data partially using several calls to AgMD2_FetchMultiRecordWaveformXXX (IVI-C)or MultiRecordMeasurement.FetchMultiRecordWaveformXXX(IVI-COM) function, defining the first record, the number of records, the first point and the number of points the user wants to read at each call of the function.

Example using AgMD2 IVI-C

Reading Int16 data in two blocks of points/2 length each (with NUM_RECORDS =1)

status = AgMD2_QueryMinWaveformMemory(session, 16, NUM_RECORDS, 0, points/2, &arraySize);

dataArray = (ViInt16*)malloc((size_t)arraySize * sizeof(ViInt16));

// Perform the acquisition.

printf("Performing acquisition\n");

status = AgMD2_InitiateAcquisition(session);

status = AgMD2_WaitForAcquisitionComplete(session, timeoutInMs);

if (status)

{

}

// Fetch the acquired data in array.

status = AgMD2_FetchMultiRecordWaveformInt16(session, "Channel1", 0, NUM_RECORDS, 0, points/2, arraySize, dataArray, &waveformArrayActualSize, &actualRecords, actualPoints, firstValidPoint, initialXOffset, initialXTimeSeconds, initialXTimeFraction, &xIncrement,&scaleFactor,&scaleOffset);

if (status)

{

}

status = AgMD2_FetchMultiRecordWaveformInt16(session, "Channel1", 0, NUM_RECORDS, points/2, points/2, arraySize, dataArray, &waveformArrayActualSize, &actualRecords, actualPoints, firstValidPoint, initialXOffset, initialXTimeSeconds, initialXTimeFraction, &xIncrement,&scaleFactor,&scaleOffset);

if (status)

{

}

Example using AgMD2 IVI-COM (C-sharp)

Reading Int32 data in two blocks (with NUM_RECORDS =1)

long firstRecord = 0;

long offsetWithinRecord = 0;

long actualRecords = 0;

long[] actualPoints = null;

long[] firstValidPoint = null;

double[] initialXOffset = null;

double[] initialXTimeSeconds = null;

double[] initialXTimeFraction = null;

double xIncrement = 0;

double scaleFactor = 0;

double scaleOffset = 0;

long numRecordsToRead = 1;

long numPointToRead = agDrvr.Acquisition.RecordSize/2;

long arrayElements = agDrvr.Acquisition3.QueryMinWaveformMemory(32, numRecordsToRead, 0, agDrvr.Acquisition.RecordSize);

Int32[] waveformArray1 = new Int32[arrayElements];

//To first the first numPointToRead data:

agDrvr.Channels.get_Item(channel).MultiRecordMeasurement.FetchMultiRecordWaveformInt32(

firstRecord,

numRecordsToRead,

offsetWithinRecord,

numPointToRead,

ref waveformArray1,

ref actualRecords,

ref actualPoints,

ref firstValidPoint,

ref initialXOffset,

ref initialXTimeSeconds,

ref initialXTimeFraction,

ref xIncrement,

ref scaleFactor,

ref scaleOffset);

Int32[] waveformArray2 = new Int32[arrayElements];

//To first the last numPointToRead data:

agDrvr.Channels.get_Item(channel).MultiRecordMeasurement.FetchMultiRecordWaveformInt32(

firstRecord,

numRecordsToRead,

offsetWithinRecord+numPointToRead,

numPointToRead,

ref waveformArray2,

ref actualRecords,

ref actualPoints,

ref firstValidPoint,

ref initialXOffset,

ref initialXTimeSeconds,

ref initialXTimeFraction,

ref xIncrement,

ref scaleFactor,

ref scaleOffset);


How to load a new firmware?

The on-board FPGAs (field-programmable gate arrays) contain processor logic needed to efficiently execute several crucial functions. They will be automatically programmed at startup before calibration.


Migrate from Acqiris or MD1 to MD2

You are here: M9203A User Manual > Programming Information > How To ... > Migrate from Acqiris or MD1 to MD2

How to migrate from Acqiris or MD1 to MD2?

Migration from MD1 to MD2

The procedure is described in AgMD2 Software migration note available from Windows Start Menu > Keysight MD2 digitizer > AgMD2 Software Migration.

Migration from Acqiris to MD2

First, the environment settings and libraries should be redefined. Details can be found in following documentations:

AgMD2 IVI-COM Driver > Programming with the IVI-COM Driver in Various ADEs

AgMD2 IVI-C Driver > Programming with the IVI-C Driver in Various ADEs

Secondly, user code should be updated: For each "Acqrs_" and "AcqrsD1_" functions, user need to find the equivalent in the AgMD2_ functions. Note that in some cases it might be required to use a group of functions to emulate the previous one.

For a cross-reference table between Acqiris API and AgMD2 function or for any question, please contact Keysight technical support for assistance at acqiris_support@keysight.com.


ApplySetup

The MD2 driver implements the following consistent behavior: No configuration change is applied immediately to the instrument hardware. Specifically, this means that setting any property/attribute only changes the 'setup' in the driver, and an explicit call to ApplySetup is required to implement the change in the instrument hardware.

There are some exceptions for 'actions': being methods/functions that perform an action which e.g. modifies also the instrument's state.

The following methods WILL perform an implicit ApplySetup before the actual action:

Actions with implicit ApplySetup

Method name | Description
SelfTest | To insure the instrument is actually in the desired state before doing the self test.
SelfCalibrate | To insure the instrument is actually in the desired state before self-calibrating.
Initiate | To apply the configured setup to the instrument hardware before starting the measurement.
Read | All Read methods start by performing an Initiate followed by Wait and then Fetch.
Reset | Places the instrument in a known state and configures instrument options on which the IVI specific driver depends.
ResetWithDefaults | Does the equivalent of Reset and then, (1) disables class extension capability groups, (2) sets attributes to initial values defined by class specs, and (3) configures the driver to option string settings used when Initialize was last executed.


Known issues for MATLAB users

The following table details the supported platforms and known issues for MATLAB drivers:

MATLAB Version | Windows 32-bit |  | Windows 64-bit
 | IVI-C | IVI-COM | IVI-C | IVI-COM
MATLAB R2012b 32-bit | Ok See notes: 2, 3, 4. | Ok See note 1. | Ok See notes: 2, 3, 4. | Ok See note 1.
MATLAB R2012b 64-bit | Not applicable | Not applicable | Ok See notes 2, 3. | Not supported
MATLAB R2013a to R2014b (32-bit) | Ok See notes: 3, 4. | Ok See note 1. | Ok See notes: 3, 4. | Ok See note 1.
MATLAB R2013a to R2014b (64-bit) | Not applicable | Not applicable |  | Not supported
MATLAB R2015a or b (32-bit) | Not supported | Not supported
MATLAB R2015a or b (64-bit) | Not applicable | Not applicable

  1. IVI-COM: The IviDigitizer class FetchMultiRecordWaveform functions do not work. Please use the MD2 driver specific equivalent functions instead.
  2. IVI-C: The function name must be given in lower case through the invoke function. MATLAB R2013a contains a fix for this issue.
  3. IVI-C: The command 'mex -setup' has to be run each time when switching from a version of MATLAB to another to avoid issues.
  4. IVI-C: When running the 'mex -setup' command, another supported compiler has to be selected than the one provided by MathWorks (Lcc). Otherwise Int64 attributes will not be supported.

    MATLAB R2016 doesn't plan the support of IVI-COM 32-bit.


Utilities

This section describes supplied programs which may be used to configure various aspects of your instruments.

Firmware Upgrade Utility

Option Upgrade Utility


Firmware Update Utility (AgMD2UpdateFirmware)

The AgMD2UpdateFirmware programming utility (AgMD2UpdateFirmware.exe) is used to load firmware to your Keysight instrument.

AgMD2UpdateFirmware General Information

The command line tool used is AgMD2UpdateFirmware.exe

Syntax:

AgMD2UpdateFirmware.exe <ModuleResourceName> <DestinationStore> <filename>

The ModuleResourceName value is the VISA resource string.

The DestinationStore value should be ConfigFlashCtrlFpga.

All of the listed parameters are mandatory.

Filename conventions

Files with the ".mcs" extension contain instrument operating firmware generated by Keysight, but may be used on any instrument of the appropriate model type.

If one or more spaces appear in the filename or path, the double quotes are required on the filename string as shown in the examples below.

It is not possible for the utility to check that the file is suitable for the FPGA Closed Field Programmable Gate Array / CPLD of the specified device, so please use this mode carefully. Programming a device with the incorrect firmware file may render it unusable.
However, as long as the device has not yet been re-booted (power cycled) it will be possible to re-write the correct file. Conversely, if the device has been incorrectly programmed and subsequently re-booted, it will be necessary to return it to an Keysight Service Center for recovery.

Instructions:

Open a Command Prompt Window (Start > Programs > Accessories > Command Prompt) and run the following commands:.

cd C:\Program Files\Keysight\MD2\Bin
AgMD2UpdateFirmware.exe PXIx::0::0::INSTR ConfigFlashCtrlFpga "C:\Program Files\IVI Foundation\IVI\Drivers\AgMD2\Firmware\M9203A CTRL_DPULX2.mcs"

The control file depends on the model type (for example M9203A CTRL_DPULX2.mcs)

PXIx::0::0::INSTR is the VISA resource string, it must match the resource string as shown in the Keysight Connection Expert. You can find the VISA resource string in the Keysight Connection Expert by clicking on the M9203A and then on the Instrument Properties tab (see M9203A Startup Guide > "Step 5: Verify Operation of the M9203A Module" for more information).

"Firmware update successful" is displayed on the screen, once the programming is completed,

Power cycle the chassis to take into account the modification.

If you are using a remote controller, power cycle the host PC. It is often necessary to wait until the chassis and its modules have completed their start-up sequence before proceeding to reboot or power-up the host controller.

Check the module front panel indicators – after the boot process the STATUS LED should be green, and no other LED lits.


Customer Options Upgrade Utility

The Customer Options Upgrade utility (KtMD2LoadEeprom) allows to upgrade the digitizer with new customer options, loading the customer option EEPROM file.

The command line tool used is KtMD2LoadEeprom.exe

Syntax:

KtMD2LoadEeprom.exe <ModuleResourceName> <SourceFile>

The ModuleResourceName value is the VISA resource string.

If one or more spaces appear in the filename or path, the double quotes are required on the filename string.


FAQs

Q. What is Coherent Sampling

A. Coherent Sampling refers to the relationship between the input frequency, sampling frequency, number of cycles in the sampled set and the number of samples. With coherent sampling one is assured that the signal power in an FFT is contained within one FFT bin (assuming a single input tone).

The condition for coherent sampling is given by:

For example if we have Msamples = 211, and fs = 100e6, and we expect and input frequency close to fs/2, let's say fin = 44 MHz, then Ncycles = 901.12 which is close to an integer. We could therefore round down to Ncycles = 901 and we would get fin = 43.994140625 Mhz, which is an input frequency that satisfies coherent sampling.

The integer number should be chosen carefully. We have three possible types of integers, even, odd, and prime. Even is not a good idea since we would hit the same code every Msamples, where M can be much less than N. Odd is a better idea since it takes longer to hit the same code. According to some sources a prime number of cycles is the best (with the exception of the prime 2) because it takes a long time before the same code repeats.

——————————————————————

Q. How to manage the internal temperature?

A. The operating temperature of the M9203A is typically specified from 0°C to +50°C (see datasheet for details). This is the internal ambient temperature at intake of the digitizer's fan.

The internal temperature read from the MD2 SFP Closed Soft Front Panel or using the function BoardTemperature (IVI-COM) / AgMD2_QueryBoardTemperature (IVI-C) is the DPU Closed Digital Processing Unit FPGA Closed Field Programmable Gate Array core Temperature (or junction temperature Tj). This Temperature should stay below 85°C to guarantee FPGA Closed Field Programmable Gate Array proper operating.

The digitizer's fan speed is controlled with the internal temperature, it maintains the FPGA Closed Field Programmable Gate Array core temperature below 85°C.

Note that the temperatures in channel ADCs (given by ChannelTemperature (IVI-COM) / AgMD2_ChannelTemperature (IVI-C)) can reach 100°C in standard operating mode.

——————————————————————

Installation of a M9203A in a M9018A PXIe 18-Slot chassis:

A maximum of eight M9203A modules can be installed in a M9018A PXIe 18-Slot Chassis.

Q. I've installed my M9203A in a M9018A PXIe 18-Slot chassis, but it's not visible from Keysigth connection expert on the external host PC, what should I do?

A. This problem can happen if the chassis is not in the default configuration (1x8). Please refer to chassis documentation:

http://literature.cdn.keysight.com/litweb/pdf/M9018-90005.pdf, see section Selecting a Link Configuration.

Q. How to maximize data throughput performance for M9203A digitizer in a M9018A PXIe 18-slot chassis?

A. Please note that to offer the maximum data throughput, the M9203A digitizer should be installed in a x8 slot, i.e. in slot 2, 5, 11 or 18.


Trigger

Normally the trigger settings applied to the digitizer are used to determine the time at which the device will stop acquiring data. The various trigger settings are outlined below.

Trigger Source

Trigger Impedance & Coupling

The M9203A has a fixed 50 Ω termination impedance with DC coupling.

Trigger Input Bandwidths

The bandwidth of the channel triggers is .

The external trigger inputs have a bandwidth from DC to 2 GHz.

Trigger Level

The trigger level specifies the voltage at which the selected trigger source will produce a valid trigger. All trigger circuits have sensitivity levels that must be exceeded in order for reliable triggering to occur.

Edge Trigger Slope

The trigger slope defines which one of the two possible transitions will be used to initiate the trigger when it passes through the specified trigger level. Positive slope indicates that the signal is transitioning from a lower voltage to a higher voltage. Negative slope indicates the signal is transitioning from a higher voltage to a lower voltage.

Trigger Time Interpolator

The digitizer also measures and stores the arrival time of each trigger using the information from the on board Trigger Time Interpolator (TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time).). This information is essential for determining the precise relation between the trigger and the digitized samples of the signal. The TTI Closed Trigger Time Interpolator:- A function that accurately measures the time from the trigger point to the first sample point. The TTI permits accurate positioning of the trigger signal with respect to the internal clock (sampling time). resolution determines the resolution of the trigger time stamps.

Pre- and Post-Trigger Delay

To increase trigger flexibility a pre- or post-trigger delay can be applied to the trigger position.

The amount of pre-trigger delay can be adjusted between 0 and 100% of the acquisition time window (i.e. sampling interval x number of samples), whereas the post-trigger delay can be adjusted within the time interval from 0 to (232 – 1) * block_size (samples), where

Pre- or post-trigger delays are just different aspects of the same trigger positioning parameter:

  • The condition of 100% pre-trigger indicates that all data points are acquired prior to the trigger, i.e. the trigger point is at the end of the acquired waveform.
  • The condition of 0% pre-trigger (which is identical to a post-trigger of 0%) indicates that all data points are acquired immediately after the trigger, i.e. the trigger point is at the beginning of the acquired waveform.
  • The condition of a non-zero post-trigger delay indicates that the data points are acquired after the trigger occurs, at a time that corresponds to the post-trigger delay, i.e. the trigger point is before the acquired waveform.

The digitizer hardware accepts pre- and post-trigger adjustments in increments of 16 samples. By definition post-trigger settings are a positive number and pre-trigger settings are a negative number.

Thus it is only natural that the software drivers treat pre- and post-trigger delays as a single parameter in seconds that can vary between

–NbrSamples * SamplingInterval (100% pre-trigger)

and +maxPostTrigSamples * SamplingInterval (max post-trigger).